8 Bit Booth Multiplier Verilog Code

                                      Verilog Code

module BoothMulti(X, Y, Z
    );

      input signed [7:0] X, Y;
       output signed [31:0] Z;
       reg signed [31:0] Z;
       reg [1:0] temp;
       integer i;
       reg E1;
       reg [7:0] Y1;
       always @ (X, Y)
       begin
       Z = 31'd0;
       E1 = 1'd0;
       for (i = 0; i < 4; i = i + 1)
       begin
       temp = {X[i], E1};
       Y1 = - Y;
  case (temp)
       2'd2 : Z [31 : 15] = Z [31 : 15] + Y1;
       2'd1 : Z [31: 15] = Z [31 : 15] + Y;
       default : begin end
       endcase
       Z = Z >> 1;
  
       Z[31] = Z[30];
  
 
       E1 = X[i];
           end
       if (Y == 16'd32)
 
 
           begin
               Z = - Z;
           end
 
       end
 
  
endmodule

Test Bench

module BoothTB;

    // Inputs
    reg [7:0] X;
    reg [7:0] Y;

    // Outputs
    wire [31:0] Z;

    // Instantiate the Unit Under Test (UUT)
    BoothMulti uut (
        .X(X),
        .Y(Y),
        .Z(Z)
    );

    initial begin
        // Initialize Inputs
        X = 0;
        Y = 0;

        // Wait 100 ns for global reset to finish
        #100;
        X=-5;
          Y=7;
        // Add stimulus here

    end
 
endmodule

   

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